1. Work closely with designer and architect to write comprehensive verification test plans and tests at block /IP, and full chip level.
2. Develop test benches and verification infrastructure from scratch for a MCU (Arm based) system for RTL pre silicon verification. Develop the needed regression environment and capability and own regression related tasks.
3. Use system Verilog to build and test UVM based environment at RTL and logic gate level. Environment could be used to verify Verilog code at block, full chip to do random tests and/or pre written function tests
4. Drive and participate in verification plan reviews of owned and/or other blocks
5. Generate and track coverage metrics and present to management team. File and track bugs in bug tracking tool till resolution.
6. Develop power/performance related tests to evaluate the power/performance value.
7. Will participate in FPGA development and verification on flow / board development, synthesis, and final verification.
1. BSEE or MSEE (preferred) with 2+ years of directly related industry experience in ASIC/SoC/FPGA Verification.
2. Should have worked on developing/implementing test plans at the block/chip-level for a multi-million-gate complex SOC.
3. Fluent in System Verilog/C++/C, Verilog, and scripting languages. Demonstrated competency with Perl/Python scripting language(s) is desirable
4. Hands-on experience on verification methodologies in OVM/UVM with System Verilog for 2+ years, including writing environments from scratch.
5. Familiar with verification automation requirements (assertion, checker, monitor, regression …etc), scheme, development, implementation, random test development, coverage driven verification is highly desirable.
6. Silicon validation experience is good plus.
7. Good communication skills, team working spirits.